A system-on-chip (SoC) usually includes one or more bus masters and bus slaves. Typically, the bus masters and the bus slaves operate at different frequencies requiring different bandwidths. Therefore, the SoC includes a high bandwidth bus, such as an advanced high-performance bus (AHB), to which bus slaves (e.g., peripherals, modules, and/or interfaces) operating at a high bandwidth are connected, and a low bandwidth bus, such as an advanced peripheral bus (APB), to which bus slaves operating at a low bandwidth are connected. However, when the bus slaves operating at the low bandwidth are accessed via the high bandwidth bus, the overall system bandwidth may be significantly reduced due to higher access latency. Especially, this can be an issue during read accesses as the write accesses can be buffered to isolate from such bandwidth reduction issues. For example, in a read access, until the requested data is fetched from the bus slave(s) operating at the low bandwidth, the bus masters may not issue another read/write transaction request and the high bandwidth bus can be virtually choked till the issued read transaction is completed. This can result in loss of throughput of several cycles in the bus masters due to the peripheral latency and inactivity on the high bandwidth bus.